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MCP9800/1/2/3
4.1.6
ACKNOWLEDGE (ACK)
Address Byte
Each receiving device, when addressed, is obliged to
SCL
1
2
3
4
5
6
7
8
9
generate an ACK bit after the reception of each byte.
The master device must generate an extra clock pulse
SDA
1
0
0
1 A2 A1 A0
A
C
K
for ACK to be recognized.
The acknowledging device pulls down the SDA line for
Start
Address
Code
Slave
Address
R/W
t SU-DATA before the low-to-high transition of SCL from
the master. SDA also needs to remain pulled down for
t H-DATA after a high-to-low transition of SCL.
PIC18FXXXX Response
During read, the master must signal an End-of-Data
FIGURE 4-1:
Device Addressing.
(EOD) to the slave by not generating an ACK bit (NAK)
once the last bit has been clocked out of the slave. In
4.1.5 DATA VALID
After the Start condition, each bit of data in
transmission needs to be settled for a time specified by
t SU-DATA before SCL toggles from low-to-high (see
“Serial Interface Timing Specifications” on Page 5 ).
DS21909D-page 12
this case, the slave will leave the data line released to
enable the master to generate the Stop condition.
? 2010 Microchip Technology Inc.
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